Is PowerPC still relevant?
Who uses PowerPC nowadays?
I had this question whenever I saw LLVM bug tickets or code that mention “PowerPC”. Hopefully this Quora Q&A answers my question:
Relevant quotes:
IBM uses a follow-on architecture, POWER, in its supercomputers and mainframes.
PowerPC is a dead architecture which is no longer in active development because the AIM alliance no longer exists. You might be thinking of the IBM POWER ISA which was derived from PowerPC.
PowerPC is a very effective processor for high-performance server-based computing.
Aha! LLVM codegen tests like llvm/test/CodeGen/PowerPC/fma-mutate.ll are still relevant for testing the IBM Power ISA.
Power ISA v3.1 (latest spec) was released in 2020.
People still use the term powerpc, but to refer to Power ISA I guess 🤷♂️
Documentation for Power ISA
There is an official IBM website for hosting info related to the Power ISA.
The documents seem to be hosted by Box cloud, but at the moment the Box refuses to provide a download of the files for some reason 😰
Hopefully I found another link that hosts the Power ISA v3.1 book (pdf).
Learning Power ISA Instructions
Below are several Power ISA instructions I had to learn to fix a PowerPC codegen test at work.
vspltisw: Vector Splat Immediate Signed Word
vspltisw 2, -3 does the following:
# VSR = Vector-Scalar Register. 64 VSRs available. VSR[32]~VSR[63] are for signed integers.
# EXTS32 = Sign extend to 32 bits
for (int i : [0, 3])
VSR[2 + 32].word[i] = EXTS32(-3)
bc: Branch Conditional
bc 12, 2, .LBB0_2 does the following:
# CR = 32-bit "Condition Register"
# BI = 2
# BO = 12 (or 01100B)
BO determines the condition under which the branch is taken.
In this case, "branch if CR[BI] == 1"
if (CR[2] == 1)
goto(.LBB0_2)
xstsqrtdp: VSX Scalar Test for software Square Root Double-Precision
xstsqrtdp 0, 1 does the following:
# CR = 32-bit "Condition Register"
# VSR = Vector-Scalar Register.
Update CR[0] after inspecting VSR[1].dword[0] (double-precision floating-point value)
xsmuldp : VSX Scalar Multiply Double-Precision
xsmuldp 2, 1, 0 does the following:
# Simple double-precision multiplication using VSX registers.
VSR[2].dword[0] = VSR[1].dword[0] x VSR[0].dword[0]
addis : Add Immediate Shifted
addis 3, 2, .LCPI0_0@toc@ha does the following:
# GPR : General Purpose Register
GPR[3] = GPR[2] + LSHIFT ( .LCPI0_0@toc@ha , 16 )
lfs : Load Floating-Point Single
lfs 4, .LCPI0_1@toc@l(3) does the following:
# FRT: Floating-Point Register (32 FRTs available)
FRT(4) = *( EXTS64(.LCPI0_1@toc@l) + GPR[3] )
xvcvsxwdp : VSX Vector Convert Signed Word to Double-Precision format
xvcvsxwdp 2, 34 does the following:
for i in [0, 1] {
VSR[2].dword[i] = CAST_I32_TO_F64 ( VSR[34].dword[i].word[0] )
}
fmr : Floating Move Register
fmr 5, 2 does the following:
# Store FRT[2] to FRT[5]
FRT[5] = FRT[2]
xsmaddadp & xsmaddmdp : VSX Scalar Multiply-Add Double-Precision
Type-A : xsmaddadp
xsmaddadp 5, 3, 0 does the following:
VSR[5].dword[0] += VSR[3].dword[0] x VSR[0].dword[0]
Type-M : xsmaddmdp
xsmaddmdp 2, 0, 3 does the following:
VSR[2].dword[0] = VSR[0].dword[0] x VSR[2].dword[0] + VSR[3].dword[0]
Short Comments on Power ISA assembly
A bit unfamiliar in that, unlike X86_64 or ARM assembly where register names are used as operands, just the register indices are used as operands.